Design automation tools for integrated circuits are well known. Such tools are computer-based tools that assist design by automating procedures that would otherwise be performed manually. Such tools may employ various routing algorithms for routing interconnections between circuit components. Most routing tools for cell-based designs begin with the placement of circuit elements, cells and/or cell blocks. Placement may be manual or automated, and may include decisions on where connectors to the circuit elements, cells and/or cell blocks should be located, as well as relative orientations thereof. Various considerations may be taken into account for such decisions, such as circuit compaction/congestion, number of interconnections between components, and the like. In some cases, placement may be partially predetermined by the design of a manufacturer's existing component being employed in the circuit being designed.
After placement, global routing for the circuit design may be performed to logically determine a path for each interconnection between cells in the entire design. Routing decisions may be made based on various constraints within the context provided by the current placement of circuit elements. For example, a constraint may be to incur the shortest total length of interconnect lines between the connectors. Once a global routing has assigned a general flow of interconnect lines, a detailed routing of interconnect lines may be performed to fit the assignments.
A conventional approach to circuit design is to develop a routing solution for routing interconnections between circuit components, and then evaluate the routing solution, for example, using a constraint engine. Portions of the circuit design (nets) that do not meet specified criteria are manually rerouted, and the revised routing solution is evaluated.
Once a satisfactory routing solution has been determined, a repeater solution is then developed to assign repeaters to nets to meet timing (time signals take to travel between components) and slew (transition between voltage levels, e.g., 0 and 1) requirements. The conventional approach to determining a repeater solution is post-route, that is, after full chip routing is completed. Based on the routing topology and wire-class information of the nets, timing analysis may be performed to determine nets that do not meet timing or slew requirements. Such nets are broken up into net segments and, ideally, repeaters are inserted at such points, if available at the locations.